The invention generally relates to a selectable clocking architecture.
Referring to FIG. 1, for purposes of generating an optical signal that is transmitted through an optical fiber 20, a serializer/transmitter 5 may be used. In this manner, the transmitter 5 receives bits of data in parallel from an output register 24 and converts this parallel stream of data into an output signal that indicates a serial stream of data. The output signal, in turn, is communicated to the optical fiber 20. To accomplish this, the transmitter 5 may include an input register 12 that receives in parallel bits of data (from the output register 24) to be communicated to the fiber 20. The data that is received by the input register 12 is communicated to a parallel-to-serial conversion circuit, or selector 14, that is coupled to the fiber 20 via an electrical-to-optical (E/O) converter 11. The selector 14, in turn, generates the output signal (at its output terminal) that indicates the bits of the serial stream of data. For an optical serial bus 20, the selector 14 may be coupled to the bus 20 via an optical source 11 that is driven by the output signal from the selector 14.
Operations of the input register 12 are synchronized to edges of a clock signal (called “TXPICLK signal”) that appears on a clock signal line 19 of the transmitter 5. In this manner, in synchronization to predefined edges of the TXPICLK signal, the output register 24 receives new data and transfers stored data to the input register 12.
Because of the nature of the parallel-to-serial conversion that is performed by the selector 14, the selector 14 is clocked by a clock signal (that appears on a clock signal line 13) that has a higher frequency than the TXPICLK signal. To generate this line rate clock signal 13, clock multiplying unit circuitry (not shown) of the transmitter 5 must be implemented in the transmitter 5.
Ideally, the clock signal on the clock signal line 13 and the TXPICLK signal are synchronized, although these signals have different frequencies. However, the manner in which these clock signals are generated and the manner in which these clock signals are synchronized to each other may affect various properties that are associated with the transmitter 5. For example, the manner in which these clock signals are generated and synchronized to each other may affect the phase error, or jitter, between the clock signals, the phase margin, the power dissipated by the clock generating circuitry and the board space consumed by the clock generating circuitry.